Modern CPU chips use a variety of schemes to improve execution speeds. In addition, the security requirements of various operating systems increase the complexity of memory management requirements. Many real time systems use I/O devices that are mapped by the hardware into the memory space of the CPU. The Memory Management Unit (MMU) controls access to memory based on attributes assigned by the operating system to ranges of memory addresses. The MMU also supervises a memory cache used to buffer accesses to slower main memory. The execution unit in the CPU itself may be executing instructions in a "pipeline" which can change the order in which read and write accesses to memory addresses occur. Real time applications are sensitive to the way I/O devices are accessed by the CPU and by how I/O devices may access memory.
Memory address ranges that refer to I/O devices that are sensitive to the order and number of read and write accesses are said to be not "well behaved." The guarded attribute prevents the PPC execution unit from combining memory accesses and/or executing them out of order from the intent of the executing program. Main memory is "well behaved" and does not need the guarded attribute. If a memory range is guarded and also cacheable then the MMU may access cache memory instead of memory or a device in memory space to fulfill a read. On a Power PC the "eieio" (Enforce In-Order Execution of I/O Instruction) op-code can be used to force the pipeline to wait for an I/O instruction to complete before executing the next instruction in the program.
This is an attribute of a block of memory managed by a MMU. The PPC CPU incorporates a small block of fast ram, or cache, that is managed by the on-board MMU. The MMU tries to maintain copies of ram in the cache to speed up the processor's access to data and code. Memory mapped devices on the CPU bus must be in MMU blocks marked non-cacheable to prevent interference by the MMU. Areas of main memory that may be accessed by devices on the memory bus other than the CPU, such as DMA buffers, must also be in blocks of memory marked "non-cacheable."
This is an attribute of a block of memory managed by a MMU. A write to a memory location that is resident in the memory cache is also written to main memory at the same time instead of being delayed until the affected block is flushed from the cache back to main memory.
The compiler keyword "volatile" is a variable attribute of a pointer type that disables certain optimizations that a complier might use to speed up code. This prevents the compiler from using a register to cache a value instead of accessing the referenced location as requested in the "C" source program.
This is an attribute of a PCI bus memory address. This means that the memory accessed by the PCI Base Address Register (BAR) is "well behaved" and does not need to be guarded or non-cacheable.